1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a circuit and a method for generating a pumping voltage and a semiconductor memory apparatus using the same.
2. Related Art
In a semiconductor memory apparatus a pumping voltage (VPP) is required when storing or outputting data in order to prevent the loss of a data level. Accordingly, most semiconductor memory apparatuses have a pumping voltage generation circuit and a pumping voltage sensing device.
FIG. 1 is a schematic view of a conventional circuit 1 for generating a pumping voltage in a semiconductor memory apparatus. In FIG. 1, the pumping voltage generation circuit 1 includes first and second capacitors C1 and C2, and first through third transistors N1 through N3.
The first capacitor C1 generates a first boot voltage V_boot1 in response to an oscillator signal ‘osc’, and the second capacitor C2 generates a second boot voltage V_boot2 in response to an inverted oscillator signal ‘oscb’. The first transistor N1 outputs an external voltage VDD to a first node (nodeA) when a first transmission signal ‘trans1’ is enabled. In general, in a transistor, the level of a voltage that is output from a drain region to a source region changes depending upon the level of the voltage supplied to a gate terminal. Accordingly, the voltage level of the enabled first transmission signal ‘trans1’ represents a voltage level that allows the external voltage VDD to be most efficiently output to the first node (nodeA) without a voltage drop.
The second transistor N2 outputs the voltage of the first node (nodeA) to a second node (nodeB) when a second transmission signal ‘trans2’ is enabled. The voltage level of the enabled second transmission signal ‘trans2’ represents a voltage level that allows the voltage of the first node (nodeA) to be most efficiently output to the second node (nodeB) without a voltage drop.
The third transistor N3 outputs the voltage of the second node (nodeB) as a pumping voltage VPP when a third transmission signal ‘trans3’ is enabled. The voltage level of the enabled third transmission signal ‘trans3’ represents a voltage level that allows the voltage of the second node (nodeB) to be most efficiently output as the pumping voltage VPP without a voltage drop. The voltage levels of the enabled first through third transmission signals ‘trans1’ through ‘trans3’ are different from one another. The voltage level of the enabled first transmission signal ‘trans1’ is lowest, and the voltage level of the enabled third transmission signal ‘trans3’ is highest.
A conventional operation of the pumping voltage generation circuit 1 will be described with reference to FIG. 1.
As the first transmission signal ‘trans1’ is enabled, the first transistor N1 is turned ON. Since the external voltage VDD is supplied to the first node (nodeA), the voltage level of the first node (nodeA) transitions to the level of the external voltage VDD. When the voltage level of the first node (nodeA) becomes the level of the external voltage VDD, the first transmission signal ‘trans1’ is disabled, and the first transistor N1 is turned OFF.
The oscillator signal ‘osc’ swings between the level of the external voltage VDD and a ground level. When the oscillator signal ‘osc’ transitions to the external voltage VDD, the first capacitor C1 outputs the first boot voltage V_boot1 having the level of the external voltage VDD to the first node (nodeA). Accordingly, the voltage level of the first node (nodeA) is the sum of the first boot voltage ‘V_boot1’ and the external voltage VDD. In this case, the voltage on node A will be twice the level of the external voltage VDD.
As the second transmission signal ‘trans2’ is enabled, the second transistor N2 is turned ON, connecting the first node (nodeA) and the second node (nodeB). Thus, the voltage level of the second node (node B) will transition to the level of the voltage on node A.
The inverted oscillator signal ‘oscb’ also swings between a ground level and the level of the external voltage VDD. When the inverted oscillator signal ‘oscb’ transitions to the external voltage VDD, the second capacitor C2 outputs the second boot voltage V_boot2 having the level of the external voltage VDD to the second node (nodeB). Accordingly, the voltage level of the second node (nodeB) becomes the sum of the voltage on node A and the second boot voltage ‘V_boot2’. In this case, the voltage level on node B will be three times the level of the external voltage VDD.
As the third transmission signal ‘trans3’ is enabled, the third transistor N3 is turned ON. When the third transistor N3 is turned ON, the voltage of the second node (nodeB) is output as the pumping voltage VPP. Here, the level of the pumping voltage VPP will be three times the level of the external voltage VDD.
In the pumping voltage generation circuit 1, a pumping voltage generation efficiency changes depending upon how efficiently the second transistor N2 and the third transistor N3 transmit the various voltages. Even when the sizes of the transistors are designed to most efficiently transmit the voltages, if the sizes of the transistors change due to process variations, the efficiency of the pumping voltage generation circuit decreases compared to a designed efficiency.
The pumping voltage generation efficiency is defined by the ratio between an amount of current used by the pumping voltage generation circuit and an amount of current used by charge pumps, i.e., the first and second capacitors C1 and C2.